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Dr Mohan Das is Senior Lecturer in the School of Information technology.
+27 (0)11-950-4134
| Qualification | Year | Institution |
|---|---|---|
| PhD (Microelectronics) | 1997 | University of Durham |
| MSc (Electronics) | 1976 | University of Bombay |
| MSc (Microelectronics) | 1987 | University of Durham |
| BSc (Physics) | 1969 | University of Kerala |
| Certificate Microprocessor Technology | 1985 | University of Witwatersrand |
| Semester 1 | Semester 2 | |||
|---|---|---|---|---|
| Undergraduate | ||||
| CSE3020 | Network technology | FIT1005 | Networks and Data Communications | |
| BUS3150 | Computer facilities network management | |||
| Honours | ||||
| CSE4884 | Network design and management | |||
Research interests are:
Current Research Projects
1. Fault Tolerant Microchip Design:
We are aiming at zero defects in microchips! Is it realistic?
For microchips having more than a million transistors, it is inevitable that
one or more of it is going to fail, sooner or later. The underlying principle
of Fault Tolerant Design is to make the circuit tolerant to such faults such
that the system behaviour is not affected.
CAD tools are used for the design.
2. Wireless Networking Applications:
Wireless LANs are becoming a reality at modern work place and at public places such as Airports, which will allow laptop computers fitted with a Wi-Fi compatible network card to be linked to LAN/ WAN and Internet with out a wire link. The research will include wireless network performance and security issues.
3. Fabrication, characterization, modeling and simulation of Schottky Barrier Diodes (SBD) on silicon.
(Collaborative project with University of Pretoria)
The research is to find a material/ compound which when deposited on a p-type
silicon doped with Gallium/ Boron will yield a Schottky Barrier Diode (SBD)
with highest possible barrier height, with good temperature stability and purity
(few defects).
Refractory metals will be deposited on p-silicon. The Schottky barriers formed will be investigated. I-V, C-V and DLTS measurements will be carried out to determine the SB height, the conduction mechanism and the defect concentrations inside the SBD.
Computer models for the Schottky barrier will be developed which will assist us to explain the formation of the potential barrier. Device level simulations will be carried out using SPICE simulator to correlate the device characteristics with the models developed. Devices conforming to stringent requirements for outer space applications will be identified.